Wahid Semiconductor’s Pre-Silicon Near-Memory LPU

Why it surfaced

The page makes an unusually clear distinction between what the team says it has shipped, what it considers established, and what remains a design target: no Enlight silicon exists yet, and tape-out is planned for April 2027. Its central claim is that token-by-token decoding is limited by memory bandwidth rather than arithmetic, with 3D DRAM, KV-cache compression, and a standard DDR interface offered as the answer.

Wahid Semiconductor proposes stacking DRAM vertically on an inference processor to target 10–40 TB/s of memory bandwidth.