Observed arrival · 2026-09-18
Filosic — ONNX in. GDSII out.
A compiler that turns trained ONNX models into bit-exact RTL, FPGA bitstreams, or chip layouts using an open EDA toolchain.
○Open
⊠Login
$Paid
†Ads
✦Pretty
●Pro
◎Niche
◉Human
⚑Risk
ƒJS
- For
- FPGA developers and open-chip hardware researchers
- Worth noticing
- The homepage reports one shared engine at roughly 174,000 Sky130 cells, versus roughly 4 million for a per-layer design.
Field notes
The documented flow assigns weights to synthesized case logic and places activations and line buffers in a banked Sky130 SRAM macro. The homepage reports a calibrated INT8 ResNet8 result, a 50 MHz Nexys A7 test path, and approximately 230 MHz post-route Fmax on VU47P. It names the open tools used at each stage, including Yosys, OpenROAD, KLayout, Magic, Sky130, FreePDK45, and ngspice.
Observed signals
Read the marks
Editorial observations of this landing page, not a rating.
○OpenPublic substance visible
⊠LoginAccess appeared gated
✦PrettyNotable craft visible
●ProPolished or operationally mature
◎NicheUnusually specific use
One card from the complete issue