Observed arrival · 2026-10-16
Nishkam: Verilog practice to chip layout
Nishkam offers free browser-based Verilog practice problems and a chip-design studio that shows a design’s path from RTL code to layout.
○Open
⊠Login
$Paid
†Ads
✦Pretty
●Pro
◎Niche
◉Human
⚑Risk
ƒJS
- For
- IC design learners and practicing RTL designers
- Worth noticing
- Its checker uses Yosys’ SAT solver to compare designs across every input sequence and cycle, rather than relying on sampled tests.
Field notes
The practice flow asks users to write Verilog, submit it, and inspect a counterexample cycle if their result diverges from the reference. The page names Yosys’ SAT solver as the checker and says the comparison covers every input sequence, rather than a sample of test cases. Studio is marked v0.1 and lays out a longer toolchain using open-source tools and the gf180mcuD PDK; the homepage says Studio access requires a key.
Observed signals
Read the marks
Editorial observations of this landing page, not a rating.
○OpenPublic substance visible
⊠LoginAccess appeared gated
✦PrettyNotable craft visible
●ProPolished or operationally mature
◎NicheUnusually specific use
One card from the complete issue