Observed arrival · 2026-10-27
Forgeout: circuit optimization with equivalence proofs
A browser-based tool that optimizes small logic circuits, checks that they remain equivalent, and prepares tape-out export files.
- For
- Circuit designers optimizing small combinational logic
- Worth noticing
- The GC-012 export reports a DRC-clean GDS and 15/15 Tiny Tapeout prechecks; Forgeout says no fabrication has been ordered.
Field notes
The browser build accepts Boolean expressions, CSV truth tables, or hexadecimal truth-table or netlist input, then optimizes for area, depth, or a balanced objective; its ABC pass is available only in the CLI. Results are checked exhaustively through 20 inputs and with SAT beyond that, while the published set receives a second-tool recheck. The stated support ceiling is about 500 cells and eight inputs; latch-containing circuits are refused. Exports stop at a tape-out package, not physical fabrication.
Observed signals
Read the marks
Editorial observations of this landing page, not a rating.
One card from the complete issue